1. Field of the Invention
This invention relates to microprocessor systems. In particular, the invention relates to senior loads.
2. Description of Related Art
Retirement of an instruction refers to a process of completing the execution of an instruction without any faults or interrupts and updating accordingly the architectural state of the processor. To enhance performance, it is desirable to retire an instruction prior to its execution. In pipelined architecture, an instruction typically goes through a number of pipeline stages. Early retirement of an instruction in a pipeline architecture reduces stalls of subsequent instructions in an in-order processor and provides a smooth pipeline flow. However, as pipeline architecture becomes more and more complex, implementing an efficient retirement mechanism in a pipeline architecture presents a number of challenges.
An important type of instruction is the load instruction. The load instruction essentially reads the data from memory and then writes the data into a register inside the processor. Because a register is part of the architectural state of the processor, it is important to ensure that the contents of the register are not erroneously written. When a number of load instructions enter the pipeline, problems may arise when they are executed out of order.
An instruction may be executed in order or out of order. An in-order execution processes a stream of instructions in the same order as they enter the pipeline, which is the program order. An out-of-order execution processes an instruction out of the order as it enters the pipeline stages. Although in-order execution is simpler to design, out-of-order execution sometimes is necessary to improve performance. An out-of-order execution improves performance by reducing the idle time waiting for a previous instruction in program order to be completed. However, out-of-order execution may create problems in maintaining the proper sequence of operations. This situation is especially serious for load instructions because the load instructions may erroneously overwrite the contents of the destination register if not carefully designed.
An early retirement of a load instruction in a stream of pipeline instructions may cause a problem, especially when there is a branch misprediction or other exception conditions.
Therefore there is a need in the technology to provide an efficient and accurate method to retire a load instruction without causing incorrect data writeback.
The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is executed after retiring.